Переход на версию 0.3: изменение подхода к именованию сущностей, добавление, изменение и удаление ряда функций

This commit is contained in:
Andrey Pokidov 2026-01-30 19:37:49 +07:00
parent d33daf4e2d
commit f7e41645fe
87 changed files with 4580 additions and 4051 deletions

View file

@ -7,7 +7,7 @@
// ==================== FP32 ==================== //
static const int _TEST_FP32_VERSOR_DATA_AMOUNT = 4;
static const BgcQuaternionFP32 _TEST_FP32_VERSOR_DATA_LIST[] = {
static const BGC_FP32_Quaternion _TEST_FP32_VERSOR_DATA_LIST[] = {
{ 1.0f, 2.0f, 3.0f, 4.0f },
{ 4.0f, 3.0f, 2.0f, 1.0f },
{ -1.0f, 0.0f, 0.0f, 0.0f },
@ -17,12 +17,12 @@ static const BgcQuaternionFP32 _TEST_FP32_VERSOR_DATA_LIST[] = {
void test_versor_set_values_fp32()
{
float versor_module, ratio;
BgcVersorFP32 versor;
BGC_FP32_Versor versor;
print_testing_name("bgc_versor_set_values_fp32");
print_testing_name("bgc_fp32_versor_make");
for (int i = 0; i < _TEST_FP32_VERSOR_DATA_AMOUNT; i++) {
bgc_versor_set_values_fp32(
bgc_fp32_versor_make(
_TEST_FP32_VERSOR_DATA_LIST[i].s0,
_TEST_FP32_VERSOR_DATA_LIST[i].x1,
_TEST_FP32_VERSOR_DATA_LIST[i].x2,
@ -32,28 +32,28 @@ void test_versor_set_values_fp32()
versor_module = sqrtf(versor._s0 * versor._s0 + versor._x1 * versor._x1 + versor._x2 * versor._x2 + versor._x3 * versor._x3);
if (!bgc_is_unit_fp32(versor_module)) {
if (!bgc_fp32_is_unit(versor_module)) {
print_testing_error("Versor module is not equal to one.");
return;
}
if (bgc_is_zero_fp32(_TEST_FP32_VERSOR_DATA_LIST[i].s0)) {
if (bgc_fp32_is_zero(_TEST_FP32_VERSOR_DATA_LIST[i].s0)) {
continue;
}
ratio = _TEST_FP32_VERSOR_DATA_LIST[i].s0 / versor._s0;
if (!bgc_is_zero_fp32(_TEST_FP32_VERSOR_DATA_LIST[i].x1) && !bgc_are_close_fp32(ratio, _TEST_FP32_VERSOR_DATA_LIST[i].x1 / versor._x1)) {
if (!bgc_fp32_is_zero(_TEST_FP32_VERSOR_DATA_LIST[i].x1) && !bgc_fp32_are_close(ratio, _TEST_FP32_VERSOR_DATA_LIST[i].x1 / versor._x1)) {
print_testing_error("Versor was not normalized proportionally (x1).");
return;
}
if (!bgc_is_zero_fp32(_TEST_FP32_VERSOR_DATA_LIST[i].x2) && !bgc_are_close_fp32(ratio, _TEST_FP32_VERSOR_DATA_LIST[i].x2 / versor._x2)) {
if (!bgc_fp32_is_zero(_TEST_FP32_VERSOR_DATA_LIST[i].x2) && !bgc_fp32_are_close(ratio, _TEST_FP32_VERSOR_DATA_LIST[i].x2 / versor._x2)) {
print_testing_error("Versor was not normalized proportionally (x2).");
return;
}
if (!bgc_is_zero_fp32(_TEST_FP32_VERSOR_DATA_LIST[i].x3) && !bgc_are_close_fp32(ratio, _TEST_FP32_VERSOR_DATA_LIST[i].x3 / versor._x3)) {
if (!bgc_fp32_is_zero(_TEST_FP32_VERSOR_DATA_LIST[i].x3) && !bgc_fp32_are_close(ratio, _TEST_FP32_VERSOR_DATA_LIST[i].x3 / versor._x3)) {
print_testing_error("Versor was not normalized proportionally (x3).");
return;
}
@ -65,7 +65,7 @@ void test_versor_set_values_fp32()
// ==================== FP64 ==================== //
static const int _TEST_FP64_VERSOR_DATA_AMOUNT = 4;
static const BgcQuaternionFP64 _TEST_FP64_VERSOR_DATA_LIST[] = {
static const BGC_FP64_Quaternion _TEST_FP64_VERSOR_DATA_LIST[] = {
{ 1.0, 2.0, 3.0, 4.0 },
{ 4.0, 3.0, 2.0, 1.0 },
{ -1.0, 0.0, 0.0, 0.0 },
@ -75,12 +75,12 @@ static const BgcQuaternionFP64 _TEST_FP64_VERSOR_DATA_LIST[] = {
void test_versor_set_values_fp64()
{
double versor_module, ratio;
BgcVersorFP64 versor;
BGC_FP64_Versor versor;
print_testing_name("bgc_versor_set_values_fp64");
print_testing_name("bgc_fp64_versor_make");
for (int i = 0; i < _TEST_FP64_VERSOR_DATA_AMOUNT; i++) {
bgc_versor_set_values_fp64(
bgc_fp64_versor_make(
_TEST_FP64_VERSOR_DATA_LIST[i].s0,
_TEST_FP64_VERSOR_DATA_LIST[i].x1,
_TEST_FP64_VERSOR_DATA_LIST[i].x2,
@ -90,28 +90,28 @@ void test_versor_set_values_fp64()
versor_module = sqrt(versor._s0 * versor._s0 + versor._x1 * versor._x1 + versor._x2 * versor._x2 + versor._x3 * versor._x3);
if (!bgc_is_unit_fp64(versor_module)) {
if (!bgc_fp64_is_unit(versor_module)) {
print_testing_error("Versor module is not equal to one.");
return;
}
if (bgc_is_zero_fp64(_TEST_FP64_VERSOR_DATA_LIST[i].s0)) {
if (bgc_fp64_is_zero(_TEST_FP64_VERSOR_DATA_LIST[i].s0)) {
continue;
}
ratio = _TEST_FP64_VERSOR_DATA_LIST[i].s0 / versor._s0;
if (!bgc_is_zero_fp64(_TEST_FP64_VERSOR_DATA_LIST[i].x1) && !bgc_are_close_fp64(ratio, _TEST_FP64_VERSOR_DATA_LIST[i].x1 / versor._x1)) {
if (!bgc_fp64_is_zero(_TEST_FP64_VERSOR_DATA_LIST[i].x1) && !bgc_fp64_are_close(ratio, _TEST_FP64_VERSOR_DATA_LIST[i].x1 / versor._x1)) {
print_testing_error("Versor was not normalized proportionally (x1).");
return;
}
if (!bgc_is_zero_fp64(_TEST_FP64_VERSOR_DATA_LIST[i].x2) && !bgc_are_close_fp64(ratio, _TEST_FP64_VERSOR_DATA_LIST[i].x2 / versor._x2)) {
if (!bgc_fp64_is_zero(_TEST_FP64_VERSOR_DATA_LIST[i].x2) && !bgc_fp64_are_close(ratio, _TEST_FP64_VERSOR_DATA_LIST[i].x2 / versor._x2)) {
print_testing_error("Versor was not normalized proportionally (x2).");
return;
}
if (!bgc_is_zero_fp64(_TEST_FP64_VERSOR_DATA_LIST[i].x3) && !bgc_are_close_fp64(ratio, _TEST_FP64_VERSOR_DATA_LIST[i].x3 / versor._x3)) {
if (!bgc_fp64_is_zero(_TEST_FP64_VERSOR_DATA_LIST[i].x3) && !bgc_fp64_are_close(ratio, _TEST_FP64_VERSOR_DATA_LIST[i].x3 / versor._x3)) {
print_testing_error("Versor was not normalized proportionally (x3).");
return;
}