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Переход на версию 0.3: изменение подхода к именованию сущностей, добавление, изменение и удаление ряда функций

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This commit is contained in:
Andrey Pokidov 2026-01-30 19:37:49 +07:00
parent d33daf4e2d
commit f7e41645fe
87 changed files with 4580 additions and 4051 deletions
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76
basic-geometry-test/tests/versor/versor_are_close.c
View file

@ -9,35 +9,35 @@ static const int _TEST_FP32_CLOSE_VERSOR_PAIR_AMOUNT = 10;
static const TestVersorPairFP32 _TEST_FP32_CLOSE_VERSOR_PAIR_LIST[] = {
{
{ 1.0f, 0.0f, 0.0f, 0.0f },
{ 1.0f + 0.75f * BGC_EPSYLON_FP32, 0.0f, 0.0f, 0.0f }
{ 1.0f + 0.75f * BGC_FP32_EPSYLON, 0.0f, 0.0f, 0.0f }
},
{
{ 1.0f, 0.0f, 0.0f, 0.0f },
{ 1.0f - 0.75f * BGC_EPSYLON_FP32, 0.0f, 0.0f, 0.0f }
{ 1.0f - 0.75f * BGC_FP32_EPSYLON, 0.0f, 0.0f, 0.0f }
},
{
{ 0.0f, 1.0f, 0.0f, 0.0f },
{ 0.0f, 1.0f + 0.75f * BGC_EPSYLON_FP32, 0.0f, 0.0f }
{ 0.0f, 1.0f + 0.75f * BGC_FP32_EPSYLON, 0.0f, 0.0f }
},
{
{ 0.0f, 1.0f, 0.0f, 0.0f },
{ 0.0f, 1.0f - 0.75f * BGC_EPSYLON_FP32, 0.0f, 0.0f }
{ 0.0f, 1.0f - 0.75f * BGC_FP32_EPSYLON, 0.0f, 0.0f }
},
{
{ 0.0f, 0.0f, 1.0f, 0.0f },
{ 0.0f, 0.0f, 1.0f + 0.75f * BGC_EPSYLON_FP32, 0.0f }
{ 0.0f, 0.0f, 1.0f + 0.75f * BGC_FP32_EPSYLON, 0.0f }
},
{
{ 0.0f, 0.0f, 1.0f, 0.0f },
{ 0.0f, 0.0f, 1.0f - 0.75f * BGC_EPSYLON_FP32, 0.0f }
{ 0.0f, 0.0f, 1.0f - 0.75f * BGC_FP32_EPSYLON, 0.0f }
},
{
{ 0.0f, 0.0f, 0.0f, 1.0f },
{ 0.0f, 0.0f, 0.0f, 1.0f + 0.75f * BGC_EPSYLON_FP32 }
{ 0.0f, 0.0f, 0.0f, 1.0f + 0.75f * BGC_FP32_EPSYLON }
},
{
{ 0.0f, 0.0f, 0.0f, 1.0f },
{ 0.0f, 0.0f, 0.0f, 1.0f - 0.75f * BGC_EPSYLON_FP32 }
{ 0.0f, 0.0f, 0.0f, 1.0f - 0.75f * BGC_FP32_EPSYLON }
},
{
{ 0.70710678f, 0.0f, 0.70710675f, 0.0f },
@ -54,35 +54,35 @@ static const int _TEST_FP32_DIFFERENT_VERSOR_PAIR_AMOUNT = 10;
static const TestVersorPairFP32 _TEST_FP32_DIFFERENT_VERSOR_PAIR_LIST[] = {
{
{ 1.0f, 0.0f, 0.0f, 0.0f },
{ 1.0f + 1.25f * BGC_EPSYLON_FP32, 0.0f, 0.0f, 0.0f }
{ 1.0f + 1.25f * BGC_FP32_EPSYLON, 0.0f, 0.0f, 0.0f }
},
{
{ 1.0f, 0.0f, 0.0f, 0.0f },
{ 1.0f - 1.25f * BGC_EPSYLON_FP32, 0.0f, 0.0f, 0.0f }
{ 1.0f - 1.25f * BGC_FP32_EPSYLON, 0.0f, 0.0f, 0.0f }
},
{
{ 0.0f, 1.0f, 0.0f, 0.0f },
{ 0.0f, 1.0f + 1.25f * BGC_EPSYLON_FP32, 0.0f, 0.0f }
{ 0.0f, 1.0f + 1.25f * BGC_FP32_EPSYLON, 0.0f, 0.0f }
},
{
{ 0.0f, 1.0f, 0.0f, 0.0f },
{ 0.0f, 1.0f - 1.25f * BGC_EPSYLON_FP32, 0.0f, 0.0f }
{ 0.0f, 1.0f - 1.25f * BGC_FP32_EPSYLON, 0.0f, 0.0f }
},
{
{ 0.0f, 0.0f, 1.0f, 0.0f },
{ 0.0f, 0.0f, 1.0f + 1.25f * BGC_EPSYLON_FP32, 0.0f }
{ 0.0f, 0.0f, 1.0f + 1.25f * BGC_FP32_EPSYLON, 0.0f }
},
{
{ 0.0f, 0.0f, 1.0f, 0.0f },
{ 0.0f, 0.0f, 1.0f - 1.25f * BGC_EPSYLON_FP32, 0.0f }
{ 0.0f, 0.0f, 1.0f - 1.25f * BGC_FP32_EPSYLON, 0.0f }
},
{
{ 0.0f, 0.0f, 0.0f, 1.0f },
{ 0.0f, 0.0f, 0.0f, 1.0f + 1.25f * BGC_EPSYLON_FP32 }
{ 0.0f, 0.0f, 0.0f, 1.0f + 1.25f * BGC_FP32_EPSYLON }
},
{
{ 0.0f, 0.0f, 0.0f, 1.0f },
{ 0.0f, 0.0f, 0.0f, 1.0f - 1.25f * BGC_EPSYLON_FP32 }
{ 0.0f, 0.0f, 0.0f, 1.0f - 1.25f * BGC_FP32_EPSYLON }
},
{
{ 0.707106f, 0.0f, 0.707107f, 0.0f },
@ -96,11 +96,11 @@ static const TestVersorPairFP32 _TEST_FP32_DIFFERENT_VERSOR_PAIR_LIST[] = {
void test_versor_are_close_fp32()
{
print_testing_name("bgc_versor_are_close_fp32");
print_testing_name("bgc_fp32_versor_are_close");
// Testing close pairs of versors:
for (int i = 0; i < _TEST_FP32_CLOSE_VERSOR_PAIR_AMOUNT; i++) {
if (!bgc_versor_are_close_fp32(&_TEST_FP32_CLOSE_VERSOR_PAIR_LIST[i].first, &_TEST_FP32_CLOSE_VERSOR_PAIR_LIST[i].second)) {
if (!bgc_fp32_versor_are_close(&_TEST_FP32_CLOSE_VERSOR_PAIR_LIST[i].first, &_TEST_FP32_CLOSE_VERSOR_PAIR_LIST[i].second)) {
print_testing_error("A pair of close versors was not recognized");
return;
}
@ -108,7 +108,7 @@ void test_versor_are_close_fp32()
// Testing different pairs of versors:
for (int i = 0; i < _TEST_FP32_DIFFERENT_VERSOR_PAIR_AMOUNT; i++) {
if (bgc_versor_are_close_fp32(&_TEST_FP32_DIFFERENT_VERSOR_PAIR_LIST[i].first, &_TEST_FP32_DIFFERENT_VERSOR_PAIR_LIST[i].second)) {
if (bgc_fp32_versor_are_close(&_TEST_FP32_DIFFERENT_VERSOR_PAIR_LIST[i].first, &_TEST_FP32_DIFFERENT_VERSOR_PAIR_LIST[i].second)) {
print_testing_error("A pair of different versors was recognized as close versors");
return;
}
@ -125,35 +125,35 @@ static const int _TEST_FP64_CLOSE_VERSOR_PAIR_AMOUNT = 10;
static const TestVersorPairFP64 _TEST_FP64_CLOSE_VERSOR_PAIR_LIST[] = {
{
{ 1.0, 0.0, 0.0, 0.0 },
{ 1.0 + 0.75 * BGC_EPSYLON_FP64, 0.0, 0.0, 0.0 }
{ 1.0 + 0.75 * BGC_FP64_EPSYLON, 0.0, 0.0, 0.0 }
},
{
{ 1.0, 0.0, 0.0, 0.0 },
{ 1.0 - 0.75 * BGC_EPSYLON_FP64, 0.0, 0.0, 0.0 }
{ 1.0 - 0.75 * BGC_FP64_EPSYLON, 0.0, 0.0, 0.0 }
},
{
{ 0.0, 1.0, 0.0, 0.0 },
{ 0.0, 1.0 + 0.75 * BGC_EPSYLON_FP64, 0.0, 0.0 }
{ 0.0, 1.0 + 0.75 * BGC_FP64_EPSYLON, 0.0, 0.0 }
},
{
{ 0.0, 1.0, 0.0, 0.0 },
{ 0.0, 1.0 - 0.75 * BGC_EPSYLON_FP64, 0.0, 0.0 }
{ 0.0, 1.0 - 0.75 * BGC_FP64_EPSYLON, 0.0, 0.0 }
},
{
{ 0.0, 0.0, 1.0, 0.0 },
{ 0.0, 0.0, 1.0 + 0.75 * BGC_EPSYLON_FP64, 0.0 }
{ 0.0, 0.0, 1.0 + 0.75 * BGC_FP64_EPSYLON, 0.0 }
},
{
{ 0.0, 0.0, 1.0, 0.0 },
{ 0.0, 0.0, 1.0 - 0.75 * BGC_EPSYLON_FP64, 0.0 }
{ 0.0, 0.0, 1.0 - 0.75 * BGC_FP64_EPSYLON, 0.0 }
},
{
{ 0.0, 0.0, 0.0, 1.0 },
{ 0.0, 0.0, 0.0, 1.0 + 0.75 * BGC_EPSYLON_FP64 }
{ 0.0, 0.0, 0.0, 1.0 + 0.75 * BGC_FP64_EPSYLON }
},
{
{ 0.0, 0.0, 0.0, 1.0 },
{ 0.0, 0.0, 0.0, 1.0 - 0.75 * BGC_EPSYLON_FP64 }
{ 0.0, 0.0, 0.0, 1.0 - 0.75 * BGC_FP64_EPSYLON }
},
{
{ 0.7071067811865475244, 0.0, 0.7071067811865465244, 0.0 },
@ -170,35 +170,35 @@ static const int _TEST_FP64_DIFFERENT_VERSOR_PAIR_AMOUNT = 10;
static const TestVersorPairFP64 _TEST_FP64_DIFFERENT_VERSOR_PAIR_LIST[] = {
{
{ 1.0, 0.0, 0.0, 0.0 },
{ 1.0 + 1.25 * BGC_EPSYLON_FP64, 0.0, 0.0, 0.0 }
{ 1.0 + 1.25 * BGC_FP64_EPSYLON, 0.0, 0.0, 0.0 }
},
{
{ 1.0, 0.0, 0.0, 0.0 },
{ 1.0 - 1.25 * BGC_EPSYLON_FP64, 0.0, 0.0, 0.0 }
{ 1.0 - 1.25 * BGC_FP64_EPSYLON, 0.0, 0.0, 0.0 }
},
{
{ 0.0, 1.0, 0.0, 0.0 },
{ 0.0, 1.0 + 1.25 * BGC_EPSYLON_FP64, 0.0, 0.0 }
{ 0.0, 1.0 + 1.25 * BGC_FP64_EPSYLON, 0.0, 0.0 }
},
{
{ 0.0, 1.0, 0.0, 0.0 },
{ 0.0, 1.0 - 1.25 * BGC_EPSYLON_FP64, 0.0, 0.0 }
{ 0.0, 1.0 - 1.25 * BGC_FP64_EPSYLON, 0.0, 0.0 }
},
{
{ 0.0, 0.0, 1.0, 0.0 },
{ 0.0, 0.0, 1.0 + 1.25 * BGC_EPSYLON_FP64, 0.0 }
{ 0.0, 0.0, 1.0 + 1.25 * BGC_FP64_EPSYLON, 0.0 }
},
{
{ 0.0, 0.0, 1.0, 0.0 },
{ 0.0, 0.0, 1.0 - 1.25 * BGC_EPSYLON_FP64, 0.0 }
{ 0.0, 0.0, 1.0 - 1.25 * BGC_FP64_EPSYLON, 0.0 }
},
{
{ 0.0, 0.0, 0.0, 1.0 },
{ 0.0, 0.0, 0.0, 1.0 + 1.25 * BGC_EPSYLON_FP64 }
{ 0.0, 0.0, 0.0, 1.0 + 1.25 * BGC_FP64_EPSYLON }
},
{
{ 0.0, 0.0, 0.0, 1.0 },
{ 0.0, 0.0, 0.0, 1.0 - 1.25 * BGC_EPSYLON_FP64 }
{ 0.0, 0.0, 0.0, 1.0 - 1.25 * BGC_FP64_EPSYLON }
},
{
{ 0.7071067811866, 0.0, 0.7071067811865, 0.0 },
@ -212,11 +212,11 @@ static const TestVersorPairFP64 _TEST_FP64_DIFFERENT_VERSOR_PAIR_LIST[] = {
void test_versor_are_close_fp64()
{
print_testing_name("bgc_versor_are_close_fp64");
print_testing_name("bgc_fp64_versor_are_close");
// Testing close pairs of versors:
for (int i = 0; i < _TEST_FP64_CLOSE_VERSOR_PAIR_AMOUNT; i++) {
if (!bgc_versor_are_close_fp64(&_TEST_FP64_CLOSE_VERSOR_PAIR_LIST[i].first, &_TEST_FP64_CLOSE_VERSOR_PAIR_LIST[i].second)) {
if (!bgc_fp64_versor_are_close(&_TEST_FP64_CLOSE_VERSOR_PAIR_LIST[i].first, &_TEST_FP64_CLOSE_VERSOR_PAIR_LIST[i].second)) {
print_testing_error("A pair of close versors was not recognized");
return;
}
@ -224,7 +224,7 @@ void test_versor_are_close_fp64()
// Testing different pairs of versors:
for (int i = 0; i < _TEST_FP64_DIFFERENT_VERSOR_PAIR_AMOUNT; i++) {
if (bgc_versor_are_close_fp64(&_TEST_FP64_DIFFERENT_VERSOR_PAIR_LIST[i].first, &_TEST_FP64_DIFFERENT_VERSOR_PAIR_LIST[i].second)) {
if (bgc_fp64_versor_are_close(&_TEST_FP64_DIFFERENT_VERSOR_PAIR_LIST[i].first, &_TEST_FP64_DIFFERENT_VERSOR_PAIR_LIST[i].second)) {
print_testing_error("A pair of different versors was recognized as close versors");
return;
}

16
basic-geometry-test/tests/versor/versor_combine.c
View file

@ -38,14 +38,14 @@ static const TestVersorTripletFP32 _TEST_FP32_VERSOR_TRIPLET_LIST[] = {
void test_versor_combine_fp32()
{
BgcVersorFP32 versor;
BGC_FP32_Versor versor;
print_testing_name("bgc_versor_combine_fp32");
print_testing_name("bgc_fp32_versor_combine");
for (int i = 0; i < _TEST_FP32_VERSOR_TRIPLET_AMOUNT; i++) {
bgc_versor_combine_fp32(&_TEST_FP32_VERSOR_TRIPLET_LIST[i].first, &_TEST_FP32_VERSOR_TRIPLET_LIST[i].second, &versor);
bgc_fp32_versor_combine(&_TEST_FP32_VERSOR_TRIPLET_LIST[i].first, &_TEST_FP32_VERSOR_TRIPLET_LIST[i].second, &versor);
if (!bgc_versor_are_close_fp32(&versor, &_TEST_FP32_VERSOR_TRIPLET_LIST[i].result)) {
if (!bgc_fp32_versor_are_close(&versor, &_TEST_FP32_VERSOR_TRIPLET_LIST[i].result)) {
print_testing_failed();
return;
}
@ -88,14 +88,14 @@ static const TestVersorTripletFP64 _TEST_FP64_VERSOR_TRIPLET_LIST[] = {
void test_versor_combine_fp64()
{
BgcVersorFP64 versor;
BGC_FP64_Versor versor;
print_testing_name("bgc_versor_combine_fp64");
print_testing_name("bgc_fp64_versor_combine");
for (int i = 0; i < _TEST_FP64_VERSOR_TRIPLET_AMOUNT; i++) {
bgc_versor_combine_fp64(&_TEST_FP64_VERSOR_TRIPLET_LIST[i].first, &_TEST_FP64_VERSOR_TRIPLET_LIST[i].second, &versor);
bgc_fp64_versor_combine(&_TEST_FP64_VERSOR_TRIPLET_LIST[i].first, &_TEST_FP64_VERSOR_TRIPLET_LIST[i].second, &versor);
if (!bgc_versor_are_close_fp64(&versor, &_TEST_FP64_VERSOR_TRIPLET_LIST[i].result)) {
if (!bgc_fp64_versor_are_close(&versor, &_TEST_FP64_VERSOR_TRIPLET_LIST[i].result)) {
print_testing_failed();
return;
}

16
basic-geometry-test/tests/versor/versor_copy.c
View file

@ -7,7 +7,7 @@
// ==================== FP32 ==================== //
static const int _TEST_FP32_VERSOR_AMOUNT = 8;
static const BgcVersorFP32 _TEST_FP32_VERSOR_LIST[] = {
static const BGC_FP32_Versor _TEST_FP32_VERSOR_LIST[] = {
{ 1.0f, 0.0f, 0.0f, 0.0f },
{ -1.0f, 0.0f, 0.0f, 0.0f },
{ 0.182574185835f, 0.36514837167f, 0.54772255751f, 0.73029674334f },
@ -20,13 +20,13 @@ static const BgcVersorFP32 _TEST_FP32_VERSOR_LIST[] = {
void test_versor_copy_fp32()
{
BgcVersorFP32 versor;
BGC_FP32_Versor versor;
print_testing_name("bgc_versor_copy_fp32");
print_testing_name("bgc_fp32_versor_copy");
for (int i = 0; i < _TEST_FP32_VERSOR_AMOUNT; i++) {
bgc_versor_copy_fp32(&_TEST_FP32_VERSOR_LIST[i], &versor);
bgc_fp32_versor_copy(&_TEST_FP32_VERSOR_LIST[i], &versor);
if (versor._s0 != _TEST_FP32_VERSOR_LIST[i]._s0 ||
versor._x1 != _TEST_FP32_VERSOR_LIST[i]._x1 ||
@ -43,7 +43,7 @@ void test_versor_copy_fp32()
// ==================== FP64 ==================== //
static const int _TEST_FP64_VERSOR_AMOUNT = 8;
static const BgcVersorFP64 _TEST_FP64_VERSOR_LIST[] = {
static const BGC_FP64_Versor _TEST_FP64_VERSOR_LIST[] = {
{ 1.0f, 0.0f, 0.0f, 0.0f },
{ -1.0f, 0.0f, 0.0f, 0.0f },
{ 0.1825741858350553712, 0.3651483716701107423, 0.5477225575051661135, 0.7302967433402214846 },
@ -56,13 +56,13 @@ static const BgcVersorFP64 _TEST_FP64_VERSOR_LIST[] = {
void test_versor_copy_fp64()
{
BgcVersorFP64 versor;
BGC_FP64_Versor versor;
print_testing_name("bgc_versor_copy_fp64");
print_testing_name("bgc_fp64_versor_copy");
for (int i = 0; i < _TEST_FP64_VERSOR_AMOUNT; i++) {
bgc_versor_copy_fp64(&_TEST_FP64_VERSOR_LIST[i], &versor);
bgc_fp64_versor_copy(&_TEST_FP64_VERSOR_LIST[i], &versor);
if (versor._s0 != _TEST_FP64_VERSOR_LIST[i]._s0 ||
versor._x1 != _TEST_FP64_VERSOR_LIST[i]._x1 ||

56
basic-geometry-test/tests/versor/versor_is_identity.c
View file

@ -7,33 +7,33 @@
static const int _TEST_FP32_IDENTIYTY_VERSOR_AMOUNT = 9;
static const int _TEST_FP32_NON_IDENTIYTY_VERSOR_AMOUNT = 5;
static const BgcVersorFP32 _TEST_FP32_IDENTIYTY_VERSOR_LIST[] = {
static const BGC_FP32_Versor _TEST_FP32_IDENTIYTY_VERSOR_LIST[] = {
{ 1.0f, 0.0f, 0.0f, 0.0f },
{ 1.0f + 0.75f * BGC_EPSYLON_FP32, 0.0f, 0.0f, 0.0f },
{ 1.0f - 0.75f * BGC_EPSYLON_FP32, 0.0f, 0.0f, 0.0f },
{ 1.0f, 0.75f * BGC_EPSYLON_FP32, 0.0f, 0.0f },
{ 1.0f, -0.75f * BGC_EPSYLON_FP32, 0.0f, 0.0f },
{ 1.0f, 0.0f, 0.75f * BGC_EPSYLON_FP32, 0.0f },
{ 1.0f, 0.0f, -0.75f * BGC_EPSYLON_FP32, 0.0f },
{ 1.0f, 0.0f, 0.0f, 0.75f * BGC_EPSYLON_FP32 },
{ 1.0f, 0.0f, 0.0f, -0.75f * BGC_EPSYLON_FP32 }
{ 1.0f + 0.75f * BGC_FP32_EPSYLON, 0.0f, 0.0f, 0.0f },
{ 1.0f - 0.75f * BGC_FP32_EPSYLON, 0.0f, 0.0f, 0.0f },
{ 1.0f, 0.75f * BGC_FP32_EPSYLON, 0.0f, 0.0f },
{ 1.0f, -0.75f * BGC_FP32_EPSYLON, 0.0f, 0.0f },
{ 1.0f, 0.0f, 0.75f * BGC_FP32_EPSYLON, 0.0f },
{ 1.0f, 0.0f, -0.75f * BGC_FP32_EPSYLON, 0.0f },
{ 1.0f, 0.0f, 0.0f, 0.75f * BGC_FP32_EPSYLON },
{ 1.0f, 0.0f, 0.0f, -0.75f * BGC_FP32_EPSYLON }
};
static const BgcVersorFP32 _TEST_FP32_NON_IDENTIYTY_VERSOR_LIST[] = {
static const BGC_FP32_Versor _TEST_FP32_NON_IDENTIYTY_VERSOR_LIST[] = {
{ 0.0f, 1.0f, 0.0f, 0.0f },
{ 0.0f, 0.0f, 1.0f, 0.0f },
{ 0.0f, 0.0f, 0.0f, 1.0f },
{ 0.5f, 0.5f, 0.5f, 0.5f },
{ 1.0f, -1.25f * BGC_EPSYLON_FP32, 0.0f, 0.0f }
{ 1.0f, -1.25f * BGC_FP32_EPSYLON, 0.0f, 0.0f }
};
void test_versor_is_identity_fp32()
{
print_testing_name("bgc_versor_is_identity_fp32");
print_testing_name("bgc_fp32_versor_is_idle");
// Testing zero values:
for (int i = 0; i < _TEST_FP32_IDENTIYTY_VERSOR_AMOUNT; i++) {
if (!bgc_versor_is_identity_fp32(&_TEST_FP32_IDENTIYTY_VERSOR_LIST[i])) {
if (!bgc_fp32_versor_is_idle(&_TEST_FP32_IDENTIYTY_VERSOR_LIST[i])) {
print_testing_error("An identity versor was not recognized");
return;
}
@ -41,7 +41,7 @@ void test_versor_is_identity_fp32()
// Testing non-zero values:
for (int i = 0; i < _TEST_FP32_NON_IDENTIYTY_VERSOR_AMOUNT; i++) {
if (bgc_versor_is_identity_fp32(&_TEST_FP32_NON_IDENTIYTY_VERSOR_LIST[i])) {
if (bgc_fp32_versor_is_idle(&_TEST_FP32_NON_IDENTIYTY_VERSOR_LIST[i])) {
print_testing_error("A non-identity versor was recognized as an identity versor");
return;
}
@ -55,33 +55,33 @@ void test_versor_is_identity_fp32()
static const int _TEST_FP64_IDENTIYTY_VERSOR_AMOUNT = 9;
static const int _TEST_FP64_NON_IDENTIYTY_VERSOR_AMOUNT = 5;
static const BgcVersorFP64 _TEST_FP64_IDENTIYTY_VERSOR_LIST[] = {
static const BGC_FP64_Versor _TEST_FP64_IDENTIYTY_VERSOR_LIST[] = {
{ 1.0, 0.0, 0.0, 0.0 },
{ 1.0 + 0.75 * BGC_EPSYLON_FP64, 0.0, 0.0, 0.0 },
{ 1.0 - 0.75 * BGC_EPSYLON_FP64, 0.0, 0.0, 0.0 },
{ 1.0, -0.75 * BGC_EPSYLON_FP64, 0.0, 0.0 },
{ 1.0, 0.75 * BGC_EPSYLON_FP64, 0.0, 0.0 },
{ 1.0, 0.0, 0.75 * BGC_EPSYLON_FP64, 0.0 },
{ 1.0, 0.0, -0.75 * BGC_EPSYLON_FP64, 0.0 },
{ 1.0, 0.0, 0.0, 0.75 * BGC_EPSYLON_FP64 },
{ 1.0, 0.0, 0.0, -0.75 * BGC_EPSYLON_FP64 }
{ 1.0 + 0.75 * BGC_FP64_EPSYLON, 0.0, 0.0, 0.0 },
{ 1.0 - 0.75 * BGC_FP64_EPSYLON, 0.0, 0.0, 0.0 },
{ 1.0, -0.75 * BGC_FP64_EPSYLON, 0.0, 0.0 },
{ 1.0, 0.75 * BGC_FP64_EPSYLON, 0.0, 0.0 },
{ 1.0, 0.0, 0.75 * BGC_FP64_EPSYLON, 0.0 },
{ 1.0, 0.0, -0.75 * BGC_FP64_EPSYLON, 0.0 },
{ 1.0, 0.0, 0.0, 0.75 * BGC_FP64_EPSYLON },
{ 1.0, 0.0, 0.0, -0.75 * BGC_FP64_EPSYLON }
};
static const BgcVersorFP64 _TEST_FP64_NON_IDENTIYTY_VERSOR_LIST[] = {
static const BGC_FP64_Versor _TEST_FP64_NON_IDENTIYTY_VERSOR_LIST[] = {
{ 0.0, 1.0, 0.0, 0.0 },
{ 0.0, 0.0, 1.0, 0.0 },
{ 0.0, 0.0, 0.0, 1.0 },
{ 0.5, 0.5, 0.5, 0.5 },
{ 1.0, 0.0, 1.25 * BGC_EPSYLON_FP64, 0.0 }
{ 1.0, 0.0, 1.25 * BGC_FP64_EPSYLON, 0.0 }
};
void test_versor_is_identity_fp64()
{
print_testing_name("bgc_versor_is_identity_fp64");
print_testing_name("bgc_fp64_versor_is_idle");
// Testing zero values:
for (int i = 0; i < _TEST_FP64_IDENTIYTY_VERSOR_AMOUNT; i++) {
if (!bgc_versor_is_identity_fp64(&_TEST_FP64_IDENTIYTY_VERSOR_LIST[i])) {
if (!bgc_fp64_versor_is_idle(&_TEST_FP64_IDENTIYTY_VERSOR_LIST[i])) {
print_testing_error("An identity versor was not recognized");
return;
}
@ -89,7 +89,7 @@ void test_versor_is_identity_fp64()
// Testing non-zero values:
for (int i = 0; i < _TEST_FP64_NON_IDENTIYTY_VERSOR_AMOUNT; i++) {
if (bgc_versor_is_identity_fp64(&_TEST_FP64_NON_IDENTIYTY_VERSOR_LIST[i])) {
if (bgc_fp64_versor_is_idle(&_TEST_FP64_NON_IDENTIYTY_VERSOR_LIST[i])) {
print_testing_error("A non-identity versor was recognized as an identity versor");
return;
}

12
basic-geometry-test/tests/versor/versor_reset.c
View file

@ -4,11 +4,11 @@
void test_versor_reset_fp32()
{
BgcVersorFP32 versor;
BGC_FP32_Versor versor;
print_testing_name("bgc_versor_reset_fp32");
print_testing_name("bgc_fp32_versor_reset");
bgc_versor_reset_fp32(&versor);
bgc_fp32_versor_reset(&versor);
if (versor._s0 != 1.0f || versor._x1 != 0.0f || versor._x2 != 0.0f || versor._x3 != 0.0f) {
print_testing_failed();
@ -20,11 +20,11 @@ void test_versor_reset_fp32()
void test_versor_reset_fp64()
{
BgcVersorFP64 versor;
BGC_FP64_Versor versor;
print_testing_name("bgc_versor_reset_fp64");
print_testing_name("bgc_fp64_versor_reset");
bgc_versor_reset_fp64(&versor);
bgc_fp64_versor_reset(&versor);
if (versor._s0 != 1.0 || versor._x1 != 0.0 || versor._x2 != 0.0 || versor._x3 != 0.0) {
print_testing_failed();

36
basic-geometry-test/tests/versor/versor_set_values.c
View file

@ -7,7 +7,7 @@
// ==================== FP32 ==================== //
static const int _TEST_FP32_VERSOR_DATA_AMOUNT = 4;
static const BgcQuaternionFP32 _TEST_FP32_VERSOR_DATA_LIST[] = {
static const BGC_FP32_Quaternion _TEST_FP32_VERSOR_DATA_LIST[] = {
{ 1.0f, 2.0f, 3.0f, 4.0f },
{ 4.0f, 3.0f, 2.0f, 1.0f },
{ -1.0f, 0.0f, 0.0f, 0.0f },
@ -17,12 +17,12 @@ static const BgcQuaternionFP32 _TEST_FP32_VERSOR_DATA_LIST[] = {
void test_versor_set_values_fp32()
{
float versor_module, ratio;
BgcVersorFP32 versor;
BGC_FP32_Versor versor;
print_testing_name("bgc_versor_set_values_fp32");
print_testing_name("bgc_fp32_versor_make");
for (int i = 0; i < _TEST_FP32_VERSOR_DATA_AMOUNT; i++) {
bgc_versor_set_values_fp32(
bgc_fp32_versor_make(
_TEST_FP32_VERSOR_DATA_LIST[i].s0,
_TEST_FP32_VERSOR_DATA_LIST[i].x1,
_TEST_FP32_VERSOR_DATA_LIST[i].x2,
@ -32,28 +32,28 @@ void test_versor_set_values_fp32()
versor_module = sqrtf(versor._s0 * versor._s0 + versor._x1 * versor._x1 + versor._x2 * versor._x2 + versor._x3 * versor._x3);
if (!bgc_is_unit_fp32(versor_module)) {
if (!bgc_fp32_is_unit(versor_module)) {
print_testing_error("Versor module is not equal to one.");
return;
}
if (bgc_is_zero_fp32(_TEST_FP32_VERSOR_DATA_LIST[i].s0)) {
if (bgc_fp32_is_zero(_TEST_FP32_VERSOR_DATA_LIST[i].s0)) {
continue;
}
ratio = _TEST_FP32_VERSOR_DATA_LIST[i].s0 / versor._s0;
if (!bgc_is_zero_fp32(_TEST_FP32_VERSOR_DATA_LIST[i].x1) && !bgc_are_close_fp32(ratio, _TEST_FP32_VERSOR_DATA_LIST[i].x1 / versor._x1)) {
if (!bgc_fp32_is_zero(_TEST_FP32_VERSOR_DATA_LIST[i].x1) && !bgc_fp32_are_close(ratio, _TEST_FP32_VERSOR_DATA_LIST[i].x1 / versor._x1)) {
print_testing_error("Versor was not normalized proportionally (x1).");
return;
}
if (!bgc_is_zero_fp32(_TEST_FP32_VERSOR_DATA_LIST[i].x2) && !bgc_are_close_fp32(ratio, _TEST_FP32_VERSOR_DATA_LIST[i].x2 / versor._x2)) {
if (!bgc_fp32_is_zero(_TEST_FP32_VERSOR_DATA_LIST[i].x2) && !bgc_fp32_are_close(ratio, _TEST_FP32_VERSOR_DATA_LIST[i].x2 / versor._x2)) {
print_testing_error("Versor was not normalized proportionally (x2).");
return;
}
if (!bgc_is_zero_fp32(_TEST_FP32_VERSOR_DATA_LIST[i].x3) && !bgc_are_close_fp32(ratio, _TEST_FP32_VERSOR_DATA_LIST[i].x3 / versor._x3)) {
if (!bgc_fp32_is_zero(_TEST_FP32_VERSOR_DATA_LIST[i].x3) && !bgc_fp32_are_close(ratio, _TEST_FP32_VERSOR_DATA_LIST[i].x3 / versor._x3)) {
print_testing_error("Versor was not normalized proportionally (x3).");
return;
}
@ -65,7 +65,7 @@ void test_versor_set_values_fp32()
// ==================== FP64 ==================== //
static const int _TEST_FP64_VERSOR_DATA_AMOUNT = 4;
static const BgcQuaternionFP64 _TEST_FP64_VERSOR_DATA_LIST[] = {
static const BGC_FP64_Quaternion _TEST_FP64_VERSOR_DATA_LIST[] = {
{ 1.0, 2.0, 3.0, 4.0 },
{ 4.0, 3.0, 2.0, 1.0 },
{ -1.0, 0.0, 0.0, 0.0 },
@ -75,12 +75,12 @@ static const BgcQuaternionFP64 _TEST_FP64_VERSOR_DATA_LIST[] = {
void test_versor_set_values_fp64()
{
double versor_module, ratio;
BgcVersorFP64 versor;
BGC_FP64_Versor versor;
print_testing_name("bgc_versor_set_values_fp64");
print_testing_name("bgc_fp64_versor_make");
for (int i = 0; i < _TEST_FP64_VERSOR_DATA_AMOUNT; i++) {
bgc_versor_set_values_fp64(
bgc_fp64_versor_make(
_TEST_FP64_VERSOR_DATA_LIST[i].s0,
_TEST_FP64_VERSOR_DATA_LIST[i].x1,
_TEST_FP64_VERSOR_DATA_LIST[i].x2,
@ -90,28 +90,28 @@ void test_versor_set_values_fp64()
versor_module = sqrt(versor._s0 * versor._s0 + versor._x1 * versor._x1 + versor._x2 * versor._x2 + versor._x3 * versor._x3);
if (!bgc_is_unit_fp64(versor_module)) {
if (!bgc_fp64_is_unit(versor_module)) {
print_testing_error("Versor module is not equal to one.");
return;
}
if (bgc_is_zero_fp64(_TEST_FP64_VERSOR_DATA_LIST[i].s0)) {
if (bgc_fp64_is_zero(_TEST_FP64_VERSOR_DATA_LIST[i].s0)) {
continue;
}
ratio = _TEST_FP64_VERSOR_DATA_LIST[i].s0 / versor._s0;
if (!bgc_is_zero_fp64(_TEST_FP64_VERSOR_DATA_LIST[i].x1) && !bgc_are_close_fp64(ratio, _TEST_FP64_VERSOR_DATA_LIST[i].x1 / versor._x1)) {
if (!bgc_fp64_is_zero(_TEST_FP64_VERSOR_DATA_LIST[i].x1) && !bgc_fp64_are_close(ratio, _TEST_FP64_VERSOR_DATA_LIST[i].x1 / versor._x1)) {
print_testing_error("Versor was not normalized proportionally (x1).");
return;
}
if (!bgc_is_zero_fp64(_TEST_FP64_VERSOR_DATA_LIST[i].x2) && !bgc_are_close_fp64(ratio, _TEST_FP64_VERSOR_DATA_LIST[i].x2 / versor._x2)) {
if (!bgc_fp64_is_zero(_TEST_FP64_VERSOR_DATA_LIST[i].x2) && !bgc_fp64_are_close(ratio, _TEST_FP64_VERSOR_DATA_LIST[i].x2 / versor._x2)) {
print_testing_error("Versor was not normalized proportionally (x2).");
return;
}
if (!bgc_is_zero_fp64(_TEST_FP64_VERSOR_DATA_LIST[i].x3) && !bgc_are_close_fp64(ratio, _TEST_FP64_VERSOR_DATA_LIST[i].x3 / versor._x3)) {
if (!bgc_fp64_is_zero(_TEST_FP64_VERSOR_DATA_LIST[i].x3) && !bgc_fp64_are_close(ratio, _TEST_FP64_VERSOR_DATA_LIST[i].x3 / versor._x3)) {
print_testing_error("Versor was not normalized proportionally (x3).");
return;
}

32
basic-geometry-test/tests/versor/versor_swap.c
View file

@ -8,13 +8,13 @@
static const int _TEST_FP32_VERSOR_AMOUNT = 3;
static const BgcQuaternionFP32 _TEST_FP32_VERSOR_LIST1[] = {
static const BGC_FP32_Quaternion _TEST_FP32_VERSOR_LIST1[] = {
{ 1.0f, 2.0f, 3.0f, 4.0f },
{ -4.0f, -3.0f, -2.0f, -1.0f },
{ 0.5f, -0.5f, -0.5f, -0.5f }
};
static const BgcQuaternionFP32 _TEST_FP32_VERSOR_LIST2[] = {
static const BGC_FP32_Quaternion _TEST_FP32_VERSOR_LIST2[] = {
{ -0.5f, 0.5f, 0.5f, 0.5f },
{ -1.0f, -2.0f, -3.0f, -4.0f },
{ 4.0f, 3.0f, 2.0f, 1.0f }
@ -22,12 +22,12 @@ static const BgcQuaternionFP32 _TEST_FP32_VERSOR_LIST2[] = {
void test_versor_swap_fp32()
{
BgcVersorFP32 versor1a, versor2a, versor1b, versor2b;
BGC_FP32_Versor versor1a, versor2a, versor1b, versor2b;
print_testing_name("bgc_versor_swap_fp32");
print_testing_name("bgc_fp32_versor_swap");
for (int i = 0; i < _TEST_FP32_VERSOR_AMOUNT; i++) {
bgc_versor_set_values_fp32(
bgc_fp32_versor_make(
_TEST_FP32_VERSOR_LIST1[i].s0,
_TEST_FP32_VERSOR_LIST1[i].x1,
_TEST_FP32_VERSOR_LIST1[i].x2,
@ -35,7 +35,7 @@ void test_versor_swap_fp32()
&versor1a
);
bgc_versor_set_values_fp32(
bgc_fp32_versor_make(
_TEST_FP32_VERSOR_LIST2[i].s0,
_TEST_FP32_VERSOR_LIST2[i].x1,
_TEST_FP32_VERSOR_LIST2[i].x2,
@ -43,10 +43,10 @@ void test_versor_swap_fp32()
&versor2a
);
bgc_versor_copy_fp32(&versor1a, &versor1b);
bgc_versor_copy_fp32(&versor2a, &versor2b);
bgc_fp32_versor_copy(&versor1a, &versor1b);
bgc_fp32_versor_copy(&versor2a, &versor2b);
bgc_versor_swap_fp32(&versor1b, &versor2b);
bgc_fp32_versor_swap(&versor1b, &versor2b);
if (versor1a._s0 != versor2b._s0 || versor1a._x1 != versor2b._x1 || versor1a._x2 != versor2b._x2 || versor1a._x3 != versor2b._x3 ||
versor2a._s0 != versor1b._s0 || versor2a._x1 != versor1b._x1 || versor2a._x2 != versor1b._x2 || versor2a._x3 != versor1b._x3) {
@ -62,12 +62,12 @@ void test_versor_swap_fp32()
void test_versor_swap_fp64()
{
BgcVersorFP64 versor1a, versor2a, versor1b, versor2b;
BGC_FP64_Versor versor1a, versor2a, versor1b, versor2b;
print_testing_name("bgc_versor_swap_fp64");
print_testing_name("bgc_fp64_versor_swap");
for (int i = 0; i < _TEST_FP32_VERSOR_AMOUNT; i++) {
bgc_versor_set_values_fp64(
bgc_fp64_versor_make(
_TEST_FP32_VERSOR_LIST1[i].s0,
_TEST_FP32_VERSOR_LIST1[i].x1,
_TEST_FP32_VERSOR_LIST1[i].x2,
@ -75,7 +75,7 @@ void test_versor_swap_fp64()
&versor1a
);
bgc_versor_set_values_fp64(
bgc_fp64_versor_make(
_TEST_FP32_VERSOR_LIST2[i].s0,
_TEST_FP32_VERSOR_LIST2[i].x1,
_TEST_FP32_VERSOR_LIST2[i].x2,
@ -83,10 +83,10 @@ void test_versor_swap_fp64()
&versor2a
);
bgc_versor_copy_fp64(&versor1a, &versor1b);
bgc_versor_copy_fp64(&versor2a, &versor2b);
bgc_fp64_versor_copy(&versor1a, &versor1b);
bgc_fp64_versor_copy(&versor2a, &versor2b);
bgc_versor_swap_fp64(&versor1b, &versor2b);
bgc_fp64_versor_swap(&versor1b, &versor2b);
if (versor1a._s0 != versor2b._s0 || versor1a._x1 != versor2b._x1 || versor1a._x2 != versor2b._x2 || versor1a._x3 != versor2b._x3 ||
versor2a._s0 != versor1b._s0 || versor2a._x1 != versor1b._x1 || versor2a._x2 != versor1b._x2 || versor2a._x3 != versor1b._x3) {